I. Field of the Disclosure
The technology of the disclosure relates generally to computer memory, and more particularly to accessing data in computer memory.
II. Background
A memory cell is a basic building block of computer data storage, which is also known as “memory.” A computer system may either read data from or write data to memory. Memory can be used to provide cache memory in a central processing unit (CPU) system as an example. Cache memory may be comprised of a tag array and a data array. The tag array performs the function of retaining an index of memory addresses stored in a higher performing data array functioning as cache memory. The data array contains the data values referenced by the index of memory addresses in the tag array. The tag array receives a memory address indicating which memory address the CPU needs to access for a read or write operations. If the received memory address matches a tag entry in the tag array, a cache hit occurs meaning the data corresponding to the memory address is present in the data array. If the received memory address does not match a tag entry in the tag array, a cache miss occurs. In this instance, the data must be retrieved from either a higher level cache or main memory.
A data array in a cache memory may be comprised of static random access memory (SRAM) bitcells to provide a SRAM data array. The SRAM data array is organized in rows and columns of SRAM bitcells, in which a single data item or bit can be stored. Access to the row containing a plurality of SRAM bitcells is controlled by a corresponding wordline for read and write operations. The wordline controls access to the SRAM bitcell for both read and write operations by selecting a desired row of SRAM bitcells for read or write operations. To read data from a SRAM bitcell, a wordline is asserted to select a desired row of SRAM bitcells. For a read operation, data read from the selected SRAM bitcell is placed on a set of corresponding bitlines. For a write operation, data to be written to the SRAM bitcell is placed on the set of corresponding bitlines for the SRAM bitcell.
It may be desired to provide memory, including cache memory, in smaller geometries in a semiconductor die as the sizes of semiconductor packaging are reduced. However, providing memory in smaller geometries can decrease semiconductor manufacturing yields. Providing memory in smaller geometries can also increase the number of defective rows or columns present in the memory. In this regard, some rows and/or columns in a data array of the memory may be used as redundant rows or columns to be used in place of defective rows or columns. A method to implement row or column redundancy within a data array of memory may include utilizing a static multiplexer system. The static multiplexer system utilizes a multiplexer for each row or column in the data array to bypass a defective row or column in the data array based on a static index indicating a defective row and/or column. For high performance or high data capacity memory, the data array may be divided into smaller data sub-arrays, also called “sub-arrays.” Each sub-array in the memory may have dedicated periphery circuits such as row decoders, write drivers, sense amplifiers, and control/clocking circuitry.
However, static multiplexers may not operate efficiently for row or column redundancy in a data array that utilizes sub-arrays. Static multiplexers may not operate efficiently, because each sub-array will have separate, dedicated row index decoding, wire routing, sense amplifiers, and control/clocking circuitry. Thus, with this memory redundancy configuration, it may be more practical or desirable to have redundant rows or columns designed or configured within each sub-array. To configure redundant rows or columns within each sub-array of a memory requires increased area for the additional redundant rows or columns to be manufactured within each sub-array in order to provide redundant rows or columns.